Modelling and optimising cache algorithms

When designing microprocessor-based systems, the performance of all components of the device being designed is of great importance. RAM is one of these systems. In order to speed up access to frequently used memory regions, caching - storing data in additional, less-capacious, faster and more expensive storage - is used. Algorithms and parameters, which determine cache functioning, influence the general speed of calculations. Besides, modern computer systems have several computing devices working simultaneously and making memory accesses independently of each other. In order to check correctness of designed cache systems and conformity of their parameters to the conceived characteristics without embodying the designed system in the real hardware, software emulation of the hardware is used. The aim of this work was to design and implement a cache system for an Intel(R) Platform Simulator(R) multiprocessor system. The main requirement for the designed system was the flexibility to change some of its parts independently of each other.