Formal Semantics and Proof Techniques for Optimizing VHDL Models - Kothanda Umamageswaran - Bøker - Springer - 9780792383758 - 30. november 1998

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Kothanda Umamageswaran
Formal Semantics and Proof Techniques for Optimizing VHDL Models Kothanda Umamageswaran 1999 edition

Name: Formal Semantics and Proof Techniques for Optimizing VHDL Models
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Author: Kothanda Umamageswaran

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Softcover reprint of the original 1st ed. 1999 edition

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Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran

1999 edition

158 pages, biography

Media	Bøker Innbunden bok (Bok med hard rygg og stivt omslag)
Utgitt	30. november 1998
ISBN13	9780792383758
Utgivere	Springer
Antall sider	158
Mål	155 × 235 × 12 mm · 435 g
Språk	Engelsk

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Kothanda Umamageswaran Formal Semantics and Proof Techniques for Optimizing VHDL Models Kothanda Umamageswaran 1999 edition